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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">Reset cause<div class="ingroups"><a class="el" href="group__group__syslib.html">SysLib       (System Library)</a> &raquo; <a class="el" href="group__group__syslib__macros.html">Macros</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Define RESET_CAUSE mask values. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga3a56e49329f1b1a8b0f3f01b23982e3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga3a56e49329f1b1a8b0f3f01b23982e3f">CY_SYSLIB_RESET_HWWDT</a>&#160;&#160;&#160;(0x0001U)</td></tr>
<tr class="memdesc:ga3a56e49329f1b1a8b0f3f01b23982e3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">A basic WatchDog Timer (WDT) reset has occurred since the last power cycle.  <a href="#ga3a56e49329f1b1a8b0f3f01b23982e3f">More...</a><br /></td></tr>
<tr class="separator:ga3a56e49329f1b1a8b0f3f01b23982e3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf98e87e2c0964035aa2098762724b30b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gaf98e87e2c0964035aa2098762724b30b">CY_SYSLIB_RESET_ACT_FAULT</a>&#160;&#160;&#160;(0x0002U)</td></tr>
<tr class="memdesc:gaf98e87e2c0964035aa2098762724b30b"><td class="mdescLeft">&#160;</td><td class="mdescRight">The fault logging system requested a reset from its Active logic.  <a href="#gaf98e87e2c0964035aa2098762724b30b">More...</a><br /></td></tr>
<tr class="separator:gaf98e87e2c0964035aa2098762724b30b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa0ecb786558344cda8cdd667d8d01801"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gaa0ecb786558344cda8cdd667d8d01801">CY_SYSLIB_RESET_DPSLP_FAULT</a>&#160;&#160;&#160;(0x0004U)</td></tr>
<tr class="memdesc:gaa0ecb786558344cda8cdd667d8d01801"><td class="mdescLeft">&#160;</td><td class="mdescRight">The fault logging system requested a reset from its Deep-Sleep logic.  <a href="#gaa0ecb786558344cda8cdd667d8d01801">More...</a><br /></td></tr>
<tr class="separator:gaa0ecb786558344cda8cdd667d8d01801"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga344f70a566a5c9a5cc155bd1e3482328"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga344f70a566a5c9a5cc155bd1e3482328">CY_SYSLIB_RESET_TC_DBGRESET</a>&#160;&#160;&#160;(0x0008U)</td></tr>
<tr class="memdesc:ga344f70a566a5c9a5cc155bd1e3482328"><td class="mdescLeft">&#160;</td><td class="mdescRight">The fault logging system requested a reset from its Test Controller or debugger asserted test.  <a href="#ga344f70a566a5c9a5cc155bd1e3482328">More...</a><br /></td></tr>
<tr class="separator:ga344f70a566a5c9a5cc155bd1e3482328"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaab329c3d83a4e66c6d77fc3dbc746a39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gaab329c3d83a4e66c6d77fc3dbc746a39">CY_SYSLIB_RESET_SOFT</a>&#160;&#160;&#160;(0x0010U)</td></tr>
<tr class="memdesc:gaab329c3d83a4e66c6d77fc3dbc746a39"><td class="mdescLeft">&#160;</td><td class="mdescRight">The CPU requested a system reset through it's SYSRESETREQ.  <a href="#gaab329c3d83a4e66c6d77fc3dbc746a39">More...</a><br /></td></tr>
<tr class="separator:gaab329c3d83a4e66c6d77fc3dbc746a39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7576c814eb77306bfda9a9edecb14a70"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga7576c814eb77306bfda9a9edecb14a70">CY_SYSLIB_RESET_SWWDT0</a>&#160;&#160;&#160;(0x0020U)</td></tr>
<tr class="memdesc:ga7576c814eb77306bfda9a9edecb14a70"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle.  <a href="#ga7576c814eb77306bfda9a9edecb14a70">More...</a><br /></td></tr>
<tr class="separator:ga7576c814eb77306bfda9a9edecb14a70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07916f36b0a552bb53f5dd507fd464ea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga07916f36b0a552bb53f5dd507fd464ea">CY_SYSLIB_RESET_SWWDT1</a>&#160;&#160;&#160;(0x0040U)</td></tr>
<tr class="memdesc:ga07916f36b0a552bb53f5dd507fd464ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle.  <a href="#ga07916f36b0a552bb53f5dd507fd464ea">More...</a><br /></td></tr>
<tr class="separator:ga07916f36b0a552bb53f5dd507fd464ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga37988ee67e1330dd35382c557497b24e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga37988ee67e1330dd35382c557497b24e">CY_SYSLIB_RESET_SWWDT2</a>&#160;&#160;&#160;(0x0080U)</td></tr>
<tr class="memdesc:ga37988ee67e1330dd35382c557497b24e"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle.  <a href="#ga37988ee67e1330dd35382c557497b24e">More...</a><br /></td></tr>
<tr class="separator:ga37988ee67e1330dd35382c557497b24e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabb8cdf49ff0e9fd12f7f8c9a8cde6d52"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gabb8cdf49ff0e9fd12f7f8c9a8cde6d52">CY_SYSLIB_RESET_SWWDT3</a>&#160;&#160;&#160;(0x0100U)</td></tr>
<tr class="memdesc:gabb8cdf49ff0e9fd12f7f8c9a8cde6d52"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle.  <a href="#gabb8cdf49ff0e9fd12f7f8c9a8cde6d52">More...</a><br /></td></tr>
<tr class="separator:gabb8cdf49ff0e9fd12f7f8c9a8cde6d52"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d320f6610ee7f457bfd8798c2da91ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga0d320f6610ee7f457bfd8798c2da91ca">CY_SYSLIB_RESET_CSV_LOSS_WAKEUP</a>&#160;&#160;&#160;(0x10000U)</td></tr>
<tr class="memdesc:ga0d320f6610ee7f457bfd8798c2da91ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">The reset has occurred on a loss of high-frequency clock.  <a href="#ga0d320f6610ee7f457bfd8798c2da91ca">More...</a><br /></td></tr>
<tr class="separator:ga0d320f6610ee7f457bfd8798c2da91ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e13f4eb0894bab7da23ff11e7bc5b35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga1e13f4eb0894bab7da23ff11e7bc5b35">CY_SYSLIB_RESET_CSV_ERROR_WAKEUP</a>&#160;&#160;&#160;(0x20000U)</td></tr>
<tr class="memdesc:ga1e13f4eb0894bab7da23ff11e7bc5b35"><td class="mdescLeft">&#160;</td><td class="mdescRight">The reset has occurred due to frequency error of high-frequency clock.  <a href="#ga1e13f4eb0894bab7da23ff11e7bc5b35">More...</a><br /></td></tr>
<tr class="separator:ga1e13f4eb0894bab7da23ff11e7bc5b35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad30b17c4bd7e48fd4628d4ee56cace84"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gad30b17c4bd7e48fd4628d4ee56cace84">CY_SYSLIB_RESET_HIB_WAKEUP</a>&#160;&#160;&#160;(0x80000000U)</td></tr>
<tr class="memdesc:gad30b17c4bd7e48fd4628d4ee56cace84"><td class="mdescLeft">&#160;</td><td class="mdescRight">The reset has occurred on a wakeup from Hibernate power mode.  <a href="#gad30b17c4bd7e48fd4628d4ee56cace84">More...</a><br /></td></tr>
<tr class="separator:gad30b17c4bd7e48fd4628d4ee56cace84"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8b0202d78f26968d02757e0b10249799"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga8b0202d78f26968d02757e0b10249799">CY_SYSLIB_RESET_XRES</a>&#160;&#160;&#160;(0x10000U)</td></tr>
<tr class="memdesc:ga8b0202d78f26968d02757e0b10249799"><td class="mdescLeft">&#160;</td><td class="mdescRight">External XRES pin was asserted.  <a href="#ga8b0202d78f26968d02757e0b10249799">More...</a><br /></td></tr>
<tr class="separator:ga8b0202d78f26968d02757e0b10249799"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5f2544aa19111ecd3159a97d7dd69cf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gad5f2544aa19111ecd3159a97d7dd69cf">CY_SYSLIB_RESET_BODVDDD</a>&#160;&#160;&#160;(0x20000U)</td></tr>
<tr class="memdesc:gad5f2544aa19111ecd3159a97d7dd69cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">External VDDD supply crossed brown-out limit.  <a href="#gad5f2544aa19111ecd3159a97d7dd69cf">More...</a><br /></td></tr>
<tr class="separator:gad5f2544aa19111ecd3159a97d7dd69cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ecd16e2c8fe061ad0d0164bc2e3b98a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga9ecd16e2c8fe061ad0d0164bc2e3b98a">CY_SYSLIB_RESET_BODVDDA</a>&#160;&#160;&#160;(0x40000U)</td></tr>
<tr class="memdesc:ga9ecd16e2c8fe061ad0d0164bc2e3b98a"><td class="mdescLeft">&#160;</td><td class="mdescRight">External VDDA supply crossed the brown-out limit.  <a href="#ga9ecd16e2c8fe061ad0d0164bc2e3b98a">More...</a><br /></td></tr>
<tr class="separator:ga9ecd16e2c8fe061ad0d0164bc2e3b98a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7798cd7ad74e8e3dc85d8d37cdb09e1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gac7798cd7ad74e8e3dc85d8d37cdb09e1">CY_SYSLIB_RESET_BODVCCD</a>&#160;&#160;&#160;(0x80000U)</td></tr>
<tr class="memdesc:gac7798cd7ad74e8e3dc85d8d37cdb09e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Internal VCCD core supply crossed the brown-out limit.  <a href="#gac7798cd7ad74e8e3dc85d8d37cdb09e1">More...</a><br /></td></tr>
<tr class="separator:gac7798cd7ad74e8e3dc85d8d37cdb09e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac21bba7fa0c24ecea50d12038a2ac136"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gac21bba7fa0c24ecea50d12038a2ac136">CY_SYSLIB_RESET_OVDVDDD</a>&#160;&#160;&#160;(0x100000U)</td></tr>
<tr class="memdesc:gac21bba7fa0c24ecea50d12038a2ac136"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overvoltage detection on the external VDDD supply.  <a href="#gac21bba7fa0c24ecea50d12038a2ac136">More...</a><br /></td></tr>
<tr class="separator:gac21bba7fa0c24ecea50d12038a2ac136"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2490062d21c8c5c7935bdf854b312858"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga2490062d21c8c5c7935bdf854b312858">CY_SYSLIB_RESET_OVDVDDA</a>&#160;&#160;&#160;(0x200000U)</td></tr>
<tr class="memdesc:ga2490062d21c8c5c7935bdf854b312858"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overvoltage detection on the external VDDA supply.  <a href="#ga2490062d21c8c5c7935bdf854b312858">More...</a><br /></td></tr>
<tr class="separator:ga2490062d21c8c5c7935bdf854b312858"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa2928ea39085b5e38fb05ed1c62d9655"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gaa2928ea39085b5e38fb05ed1c62d9655">CY_SYSLIB_RESET_OVDVCCD</a>&#160;&#160;&#160;(0x400000U)</td></tr>
<tr class="memdesc:gaa2928ea39085b5e38fb05ed1c62d9655"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overvoltage detection on the internal core VCCD supply.  <a href="#gaa2928ea39085b5e38fb05ed1c62d9655">More...</a><br /></td></tr>
<tr class="separator:gaa2928ea39085b5e38fb05ed1c62d9655"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba088d381fc6716cf9c3c83af776b567"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#gaba088d381fc6716cf9c3c83af776b567">CY_SYSLIB_RESET_OCD_ACT_LINREG</a>&#160;&#160;&#160;(0x800000U)</td></tr>
<tr class="memdesc:gaba088d381fc6716cf9c3c83af776b567"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator.  <a href="#gaba088d381fc6716cf9c3c83af776b567">More...</a><br /></td></tr>
<tr class="separator:gaba088d381fc6716cf9c3c83af776b567"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1e99c58e36c9f0d90fb108bc59de8983"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga1e99c58e36c9f0d90fb108bc59de8983">CY_SYSLIB_RESET_OCD_DPSLP_LINREG</a>&#160;&#160;&#160;(0x1000000U)</td></tr>
<tr class="memdesc:ga1e99c58e36c9f0d90fb108bc59de8983"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator.  <a href="#ga1e99c58e36c9f0d90fb108bc59de8983">More...</a><br /></td></tr>
<tr class="separator:ga1e99c58e36c9f0d90fb108bc59de8983"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a9e1a30ff804412b453df6d08552c9c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga7a9e1a30ff804412b453df6d08552c9c">CY_SYSLIB_RESET_OCD_REGHC</a>&#160;&#160;&#160;(0x2000000U)</td></tr>
<tr class="memdesc:ga7a9e1a30ff804412b453df6d08552c9c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overcurrent detection from REGHC (if present).  <a href="#ga7a9e1a30ff804412b453df6d08552c9c">More...</a><br /></td></tr>
<tr class="separator:ga7a9e1a30ff804412b453df6d08552c9c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga38c30b821ab37545d12e840729b7886b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga38c30b821ab37545d12e840729b7886b">CY_SYSLIB_RESET_PMIC</a>&#160;&#160;&#160;(0x4000000U)</td></tr>
<tr class="memdesc:ga38c30b821ab37545d12e840729b7886b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PMIC status triggered a reset.  <a href="#ga38c30b821ab37545d12e840729b7886b">More...</a><br /></td></tr>
<tr class="separator:ga38c30b821ab37545d12e840729b7886b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bfecc977d82eb0c3ac76e128f6dc5a5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga3bfecc977d82eb0c3ac76e128f6dc5a5">CY_SYSLIB_RESET_PXRES</a>&#160;&#160;&#160;(0x10000000U)</td></tr>
<tr class="memdesc:ga3bfecc977d82eb0c3ac76e128f6dc5a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PXRES triggered.  <a href="#ga3bfecc977d82eb0c3ac76e128f6dc5a5">More...</a><br /></td></tr>
<tr class="separator:ga3bfecc977d82eb0c3ac76e128f6dc5a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga762cf56f68854e559a6a93227cf55332"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga762cf56f68854e559a6a93227cf55332">CY_SYSLIB_RESET_STRUCT_XRES</a>&#160;&#160;&#160;(0x20000000U)</td></tr>
<tr class="memdesc:ga762cf56f68854e559a6a93227cf55332"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structural reset was asserted.  <a href="#ga762cf56f68854e559a6a93227cf55332">More...</a><br /></td></tr>
<tr class="separator:ga762cf56f68854e559a6a93227cf55332"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga35546f2d5563315369a1b7378245bb70"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__syslib__macros__reset__cause.html#ga35546f2d5563315369a1b7378245bb70">CY_SYSLIB_RESET_PORVDDD</a>&#160;&#160;&#160;(0x40000000U)</td></tr>
<tr class="memdesc:ga35546f2d5563315369a1b7378245bb70"><td class="mdescLeft">&#160;</td><td class="mdescRight">Indicator that a POR occurred.  <a href="#ga35546f2d5563315369a1b7378245bb70">More...</a><br /></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga3a56e49329f1b1a8b0f3f01b23982e3f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3a56e49329f1b1a8b0f3f01b23982e3f">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_HWWDT</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_HWWDT&#160;&#160;&#160;(0x0001U)</td>
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<p>A basic WatchDog Timer (WDT) reset has occurred since the last power cycle. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaf98e87e2c0964035aa2098762724b30b">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_ACT_FAULT</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_ACT_FAULT&#160;&#160;&#160;(0x0002U)</td>
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<p>The fault logging system requested a reset from its Active logic. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa0ecb786558344cda8cdd667d8d01801">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_DPSLP_FAULT</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_DPSLP_FAULT&#160;&#160;&#160;(0x0004U)</td>
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<p>The fault logging system requested a reset from its Deep-Sleep logic. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga344f70a566a5c9a5cc155bd1e3482328">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_TC_DBGRESET</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_TC_DBGRESET&#160;&#160;&#160;(0x0008U)</td>
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<p>The fault logging system requested a reset from its Test Controller or debugger asserted test. </p>
<dl class="section note"><dt>Note</dt><dd>This macro is available for devices having M33SYSCPUSS IP. </dd></dl>

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<a id="gaab329c3d83a4e66c6d77fc3dbc746a39"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaab329c3d83a4e66c6d77fc3dbc746a39">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_SOFT</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_SOFT&#160;&#160;&#160;(0x0010U)</td>
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<p>The CPU requested a system reset through it's SYSRESETREQ. </p>
<p>This can be done via a debugger probe or in firmware. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7576c814eb77306bfda9a9edecb14a70">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_SWWDT0</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_SWWDT0&#160;&#160;&#160;(0x0020U)</td>
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<p>The Multi-Counter Watchdog timer #0 reset has occurred since the last power cycle. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga07916f36b0a552bb53f5dd507fd464ea">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_SWWDT1</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_SWWDT1&#160;&#160;&#160;(0x0040U)</td>
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<p>The Multi-Counter Watchdog timer #1 reset has occurred since the last power cycle. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga37988ee67e1330dd35382c557497b24e">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_SWWDT2</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_SWWDT2&#160;&#160;&#160;(0x0080U)</td>
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<p>The Multi-Counter Watchdog timer #2 reset has occurred since the last power cycle. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gabb8cdf49ff0e9fd12f7f8c9a8cde6d52">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_SWWDT3</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_SWWDT3&#160;&#160;&#160;(0x0100U)</td>
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<p>The Multi-Counter Watchdog timer #3 reset has occurred since the last power cycle. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0d320f6610ee7f457bfd8798c2da91ca">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_CSV_LOSS_WAKEUP</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_CSV_LOSS_WAKEUP&#160;&#160;&#160;(0x10000U)</td>
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<p>The reset has occurred on a loss of high-frequency clock. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1e13f4eb0894bab7da23ff11e7bc5b35">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_CSV_ERROR_WAKEUP</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_CSV_ERROR_WAKEUP&#160;&#160;&#160;(0x20000U)</td>
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<p>The reset has occurred due to frequency error of high-frequency clock. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gad30b17c4bd7e48fd4628d4ee56cace84">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_HIB_WAKEUP</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_HIB_WAKEUP&#160;&#160;&#160;(0x80000000U)</td>
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<p>The reset has occurred on a wakeup from Hibernate power mode. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8b0202d78f26968d02757e0b10249799">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_XRES</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_XRES&#160;&#160;&#160;(0x10000U)</td>
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<p>External XRES pin was asserted. </p>
<dl class="section note"><dt>Note</dt><dd>Below macros are available for devices having CY_IP_MXS40SRSS_VERSION greater than or equal to 2. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </dd></dl>

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<a id="gad5f2544aa19111ecd3159a97d7dd69cf"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad5f2544aa19111ecd3159a97d7dd69cf">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_BODVDDD</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_BODVDDD&#160;&#160;&#160;(0x20000U)</td>
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<p>External VDDD supply crossed brown-out limit. </p>
<p>Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9ecd16e2c8fe061ad0d0164bc2e3b98a">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_BODVDDA</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_BODVDDA&#160;&#160;&#160;(0x40000U)</td>
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<p>External VDDA supply crossed the brown-out limit. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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</div>
<a id="gac7798cd7ad74e8e3dc85d8d37cdb09e1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac7798cd7ad74e8e3dc85d8d37cdb09e1">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_BODVCCD</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_BODVCCD&#160;&#160;&#160;(0x80000U)</td>
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<p>Internal VCCD core supply crossed the brown-out limit. </p>
<p>Note that this detector will detect gross issues with the internal core supply, but may not catch all brown-out conditions. </p>

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<a id="gac21bba7fa0c24ecea50d12038a2ac136"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gac21bba7fa0c24ecea50d12038a2ac136">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_OVDVDDD</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_OVDVDDD&#160;&#160;&#160;(0x100000U)</td>
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<p>Overvoltage detection on the external VDDD supply. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2490062d21c8c5c7935bdf854b312858">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_OVDVDDA</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_OVDVDDA&#160;&#160;&#160;(0x200000U)</td>
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<p>Overvoltage detection on the external VDDA supply. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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<a id="gaa2928ea39085b5e38fb05ed1c62d9655"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa2928ea39085b5e38fb05ed1c62d9655">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_OVDVCCD</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_OVDVCCD&#160;&#160;&#160;(0x400000U)</td>
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<p>Overvoltage detection on the internal core VCCD supply. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaba088d381fc6716cf9c3c83af776b567">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_OCD_ACT_LINREG</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_OCD_ACT_LINREG&#160;&#160;&#160;(0x800000U)</td>
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<p>Overcurrent detection on the internal VCCD supply when supplied by the ACTIVE power mode linear regulator. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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<a id="ga1e99c58e36c9f0d90fb108bc59de8983"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga1e99c58e36c9f0d90fb108bc59de8983">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_OCD_DPSLP_LINREG</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_OCD_DPSLP_LINREG&#160;&#160;&#160;(0x1000000U)</td>
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<p>Overcurrent detection on the internal VCCD supply when supplied by the DEEPSLEEP power mode linear regulator. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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<a id="ga7a9e1a30ff804412b453df6d08552c9c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga7a9e1a30ff804412b453df6d08552c9c">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_OCD_REGHC</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_OCD_REGHC&#160;&#160;&#160;(0x2000000U)</td>
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<p>Overcurrent detection from REGHC (if present). </p>
<p>If REGHC is not present, hardware will never set this bit.This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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<a id="ga38c30b821ab37545d12e840729b7886b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga38c30b821ab37545d12e840729b7886b">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_PMIC</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_PMIC&#160;&#160;&#160;(0x4000000U)</td>
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<p>PMIC status triggered a reset. </p>
<p>If PMIC control is not present, hardware will never set this bit. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. </p>

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<a id="ga3bfecc977d82eb0c3ac76e128f6dc5a5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3bfecc977d82eb0c3ac76e128f6dc5a5">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_PXRES</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_PXRES&#160;&#160;&#160;(0x10000000U)</td>
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<p>PXRES triggered. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. </p>

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<a id="ga762cf56f68854e559a6a93227cf55332"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga762cf56f68854e559a6a93227cf55332">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_STRUCT_XRES</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_STRUCT_XRES&#160;&#160;&#160;(0x20000000U)</td>
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<p>Structural reset was asserted. </p>
<p>This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. </p>

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<a id="ga35546f2d5563315369a1b7378245bb70"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga35546f2d5563315369a1b7378245bb70">&#9670;&nbsp;</a></span>CY_SYSLIB_RESET_PORVDDD</h2>

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          <td class="memname">#define CY_SYSLIB_RESET_PORVDDD&#160;&#160;&#160;(0x40000000U)</td>
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<p>Indicator that a POR occurred. </p>
<p>This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes. </p>

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